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MX29LV033A
32M-BIT [4M x 8] CMOS EQUAL SECTOR FLASH MEMORY
FEATURES
GENERAL FEATURES * 4,194,304 x 8 byte structure * Sixty-four Equal Sectors with 64KB each - Any combination of sectors can be erased with erase suspend/resume function * Eighteen Sector Groups - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotected function to allow code changing - Provides temporary sector group unprotected function for code changing in previously protected sector groups * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 250mA from -1V to Vcc + 1V * Low Vcc write inhibit is equal to or less than 1.4V * Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash * 2nd generation of 3V/32M Flash product - Fully compatible with MX29LV033 device PERFORMANCE * High Performance - Fast access time: 70/90ns - Fast program time: 7us/byte, 36s/chip (typical) - Fast erase time: 0.7s/sector, 35s/chip (typical) * Low Power Consumption - Low active read current: 10mA (typical) at 5MHz - Low standby current: 200nA (typical) * Minimum 100,000 erase/program cycle * 10-year data retention SOFTWARE FEATURES * Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased * Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion * Support Command Flash Interface (CFI) HARDWARE FEATURES * Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion * Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode * ACC input pin - Provides accelerated program capability PACKAGE * 40-pin TSOP
GENERAL DESCRIPTION
The MX29LV033A is a 32-mega bit Flash memory organized as 4M bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX29LV033A is packaged in 40-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV033A offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV033A has separate chip enable (CE#) and output enable (OE#) controls.
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MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV033A uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29LV033A uses a 2.7V to 3.6V VCC
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supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
matically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LV033A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC PROGRAMMING The MX29LV033A is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV033A is less than 36 seconds.
AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.
AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 35 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC SECTOR ERASE The MX29LV033A is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm auto-
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PIN CONFIGURATION
40 TSOP
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 Q7 Q6 Q5 Q4 VCC VCC A21 Q3 Q2 Q1 Q0 OE# VSS CE# A0
LOGIC SYMBOL
22 A0-A21 Q0-Q7 8
MX29LV033A
CE# OE# WE# RESET# ACC RY/BY#
PIN DESCRIPTION
SYMBOL A0~A21 Q0~Q7 CE# WE# OE# RESET# RY/BY# VCC ACC VSS NC PIN NAME Address Input 8 Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low Read/Busy Output +3.3V single power supply Hardware Acceleration Pin Device Ground Pin Not Connected Internally
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BLOCK DIAGRAM
WRITE CE# OE# WE# CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX29LV033A FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A21 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
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SECTOR (GROUP) STRUCTURE
Group SGA0 SGA1 SGA1 SGA1 SGA2 SGA2 SGA2 SGA2 SGA3 SGA3 SGA3 SGA3 SGA4 SGA4 SGA4 SGA4 SGA5 SGA5 SGA5 SGA5 SGA6 SGA6 SGA6 SGA6 SGA7 SGA7 SGA7 SGA7 SGA8 SGA8 SGA8 SGA8 SGA9 SGA9 SGA9 SGA9 SGA10 SGA10 SGA10 SGA10
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Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39
A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range(in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 270000-27FFFF
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Group SGA11 SGA11 SGA11 SGA11 SGA12 SGA12 SGA12 SGA12 SGA13 SGA13 SGA13 SGA13 SGA14 SGA14 SGA14 SGA14 SGA15 SGA15 SGA15 SGA15 SGA16 SGA16 SGA16 SGA17 Sector SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Range(in hexadecimal) 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF
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Table 1 BUS OPERATION (1)
Operation Read Write(Note 1) Standby Output Disable Reset Sector Group Protect (Note 2) Chip Unprotected (Note 2) Temporary Sector Group Unprotected CE# OE# L L L H VCC0.3V X L H X X L H L X H X WE# H L X H X L L X RESET# H H VCC0.3V H L VID VID VID Address AIN AIN X X X Sector Addresses, A6=L, A1=H, A0=L Sector Addresses, A6=H, A1=H, A0=L AIN Q0~Q7 DOUT DIN High-Z High-Z High-Z DIN, DOUT DIN, DOUT DIN
Legend: L=Logic LOW=VIL,H=Logic High=VIH,VID=12.00.5V,X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. When the ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotected functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotected" section.
BUS OPERATION(2)
Operation Read Silicon ID Manufactures Code Read Silicon ID Device Code Sector Group Protect Chip Unprotected Sector Protect Verify CE# L L L L L OE# L L VID VID L WE# H H L L H A0 L H X X X A1 L L X X H A6 X X L H X A9 VID VID VID VID VID Q0~Q7 C2H A3H X X Code(1)
Notes: 1.code=00h means unprotected, or code=01h means protected
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REQUIREMENTS FOR READING ARRAY DATA
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through the ACC function. If the system asserts VHH on ACC pin, the device will provide the fast programming time to user. This function is primarily intended to allow faster manufacturing throughput during production. Removing VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result.
STANDBY MODE
MX29LV033A can be set into Standby mode with two different approaches. One is using both CE# and RESET# pins and the other one is using RESET# pin only. When using both pins of CE# and RESET#, a CMOS Standby mode is achieved with both pins held at Vcc 0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE# and RESET# are held at VIH, but not within the range of VCC 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes. When using only RESET#, a CMOS standby mode is achieved with RESET# input held at Vss 0.3V, Under this condition the current is consumed less than 1uA (typ.). Once the RESET# pin is taken high, the device is back to active without recovery delay. In the standby mode the outputs are in the high impedance state, independent of the OE# input. MX29LV033A is capable to provide the Automatic Standby Mode to restrain power consumption during readout of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX29LV033A automatically switch themselves to low power mode when MX29LV033A addresses remain stable during access time of tACC+30ns. It is not necessary to control CE#, WE#, and OE# on the mode. Under the mode, the current consumed is typi-
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the auto-select command sequence, the device enters the auto-select mode. The system can then read auto-select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Auto-select Mode and Auto-select Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.
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cally 0.2uA (CMOS level). operations for these sector group protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL. (see Table 2) Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector group protect algorithm and waveform. MX29LV033A also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
RESET# OPERATION
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 3 for the timing diagram.
CHIP UNPROTECTED OPERATION
The MX29LV033A also features the chip unprotected mode, so that all sectors are unprotected after chip unprotected is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotected mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotected algorithm and waveform for the chip unprotected algorithm. The unprotected mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. MX29LV033A also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing.
SECTOR GROUP PROTECT OPERATION
The MX29LV033A features hardware sector group protection. This feature will disable both program and erase
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It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotected algorithm is completed. MX29LV033A provides hardware method to access the silicon ID read operation. Which method requires VID on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which apply VIL on A0 pin, the device will output MXIC's manufacture code of C2H. Which apply VIH on A0 pin, the device will output MX29LV033A device code of A3H.
TEMPORARY SECTOR GROUP UNPROTECTED OPERATION
This feature allows temporary unprotected of previously protected sector to change data in-system. The Temporary Sector Unprotected mode is activated by setting the RESET# pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as unprotected sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again.
VERIFY SECTOR GROUP PROTECT STATUS OPERATION
MX29LV033A provides hardware method for sector group protect status verify. Which method requires VID on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#, A6, and A0 pins, and sector address on A16 to A21 pins. Which the identified sector is protected, the device will output 01H. Which the identified sector is not protect, the device will output 00H.
SILICON ID READ OPERATION
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice.
DESCRIPTION Manufacturer ID:MXIC Device ID:MX29LV033A Sector Protection Verification
A21 to CE# OE# WE# A16 L L H X L L H X L L H SA
A15 to A10 X X X
A8 to A9 A7 VID X VID X VID X
A6 L L L
A5 X X X
A1 L L H
A0 L H L
Q0 to Q7 C2H A3H 01h(protected) 00h(unprotected)
L=Logic Low=VIL,H=Logic High=VIH, SA=Sector Address, X=Don't care
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DATA PROTECTION
The MX29LV033A is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE# will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.
POWER-UP SEQUENCE
The MX29LV033A powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
POWER-UP WRITE INHIBIT
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
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SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 2 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable). All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data are latched on rising edge of WE# or CE#, whichever happens first.
TABLE 2. MX29LV033A COMMAND DEFINITIONS
First Bus Command Bus Cycle Read(Note 5) Reset(Note 6) Autoselect(Note 7) Manufacturer ID Device ID Sector Protect Verify (Note 8) Byte Program Chip Erase Sector Erase Erase Suspend(Note 9) Erase Resume(Note 10) CFI Query (Note 11) 4 4 4 4 4 6 6 1 1 1 XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX AA AA AA AA AA AA AA B0 30 98 XXX XXX XXX XXX XXX XXX XXX 55 55 55 55 55 55 55 0XXXXX 0XXXXX 90 90 X00 X01 SA X02 PA XXX XXX 02 A3 00 01 PD AA AA XXX XXX 55 55 XXX 10 SA 30 1 1 Cycle Addr RA XXX Second Bus Cycle Data Addr RD F0 Third Bus Cycle Data Addr Fourth Bus Cycle Fifth Bus Cycle Sixth Bus Cycle
Data Addr Data Addr Data Addr Data
0XXXXX or 90 2XXXXX XXX XXX XXX 90 A0 80 80
Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD=Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA=Address of the sector to be erased or verified. Address bits A21-A16 uniquely select any sector.
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Notes: 1.See Table 1 for descriptions of bus operations. 2.All values are in hexadecimal. 3.Except when reading array or auto-select data, all bus cycles are write operation. 4.Address bits are don't care for unlock and command cycles, except when PA or SA is required. 5.No unlock or command cycles required when device is in read mode. 6.The Reset command is required to return to the read mode when the device is in the auto-select mode or if Q5 goes high. 7.The fourth cycle of the auto-select command sequence is a read cycle. 8.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the command sequence, address bit A21=0 to verify sectors 0~31, A21=1 to verify sectors 31~64. 9.The system may read and program functions in non-erasing sectors, or enter the auto-select mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10.The Erase Resume command is valid only during the Erase Suspend mode. 11.Command is valid when device is ready to read array data or when device is in auto-select mode.
READING ARRAY DATA
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the auto-select mode. See the "Reset Command" section, next.
quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data (also applies to SILICON ID READ during Erase Suspend). If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the se-
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected.
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Table 2 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for PROM programmers and requires VID on address bit A9. "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table for valid sector addresses. The system must write the reset command to exit the auto-select mode and return to reading array data.
BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a
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SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H. The MX29LV033A contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of A3H for MX29LV033A.
TABLE 3. SILICON ID CODE
Pins A0 A1 VIL VIL Q7 1 1 Q6 1 0 Q5 0 1 Q4 0 0 Q3 0 0 Q2 0 0 Q1 1 1 Q0 0 1 Code(Hex) C2H A3H Manufacture code VIL Device code for MX29LV033A VIH
AUTOMATIC CHIP/SECTOR ERASE COMMAND
The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automatically preprogram and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 2 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 16 for timing diagrams.
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two
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more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later , while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each successive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the timeout period resets the device to read mode. other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.
ERASE SUSPEND
This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Erase Resume, program data to, or read data from any sector not selected for erasure. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks.
ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
Table 4. Write Operation Status
Status Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read (Erase Suspended Sector) In Progress Erase Suspended Mode Erase Suspend Read Data (Non-Erase Suspended Sector) Erase Suspend Program Byte Program in Auto Program Algorithm Exceeded Time Limits Auto Erase Algorithm Erase Suspend Program Q7# Q7# 0 Q7# Data Toggle Toggle Toggle Toggle Data 0 1 1 1 Data Data N/A N/A 1 N/A N/A No Toggle Toggle N/A 1 0 0 0 0 Q7 Note1 Q7# 0 1 Q6 Toggle Toggle No Toggle Q5 Note2 0 0 0 Q3 N/A 1 Q2 RY/BY# No Toggle Toggle 0 0 1
N/A Toggle
Notes: 1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 1. Performing successive read operations from any address will cause Q6 to toggle. 3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle.
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Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data. During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement" or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE#) is asserted low. after the rising edge of the final WE# or CE#, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid
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cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. The Q5 failure condition may appear if the system tries to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a "0" back to a "1"." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, Q5 produces a "1".
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.
Q3:Sector Erase Timer
After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are
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still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. If the time between additional erase commands from the system can be less than 50us, the system need not to monitor Q3.
RY/BY#:READY/BUSY# OUTPUT
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC . If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RATINGS
Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0 C to +70 C Industrial (I) Devices Ambient Temperature (TA ). . . . . . . . . . -40 C to +85 C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS TA=-40 C to 85 C, VCC=2.7V~3.6V
Parameter ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 ICC5 Description Input Load Current (Note 1) A9 Input Load Current Output Leakage Current VCC Active Read Current (Notes 2, 3) VCC Active Write Current (Notes 2, 4, 6) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2,5) ACC Accelerated Program Current, Byte Input Low Voltage Input High Voltage Voltage for ACC Sector Protect/Unprotect and Program Acceleration Voltage for Automatic Select and Temporary Sector Unprotect Output Low Voltage Output High Voltage Test Conditions Min VIN = VSS to VCC, VCC = VCC max VCC = VCC max, A9=12.5V VOUT = VSS to VCC , VCC = VCC max CE#= VIL, 5 MHz OE# = VIH 1 MHz CE#= VIL , OE# = VIH, WE#=VIL CE#, RESET#, ACC = VCC0.3V RESET# = VSS 0.3V, ACC= VCC 0.3V VIH = VCC 0.3V; VIL = VSS 0.3V, ACC=VCC0.3V CE#=VIL, ACC pin OE#=VIH VCC pin -0.5 0.7xVcc 11.5 Typ Max 1.0 35 1.0 10 2 15 0.2 0.2 0.2 16 4 30 15 15 15 Unit uA uA uA mA mA mA uA uA uA
IACC VIL VIH VHH
5 15
VCC = 3.0 V 10%
10 30 0.8 Vcc+0.3 12.5
mA mA V V V
VID
VCC = 3.0 V 10%
11.5
12.5
V
VOL VOH1 VOH2 VLKO
IOL=4.0mA, VCC=VCC min IOH=-2.0mA, VCC=VCC min IOH=-100uA, VCC = VCC min
0.45 0.85Vcc Vcc-0.4 1.4 2.1
V V V V
Low VCC Lock-Out Voltage (Note 6)
Notes: 1. On the ACC pin only, the maximum input load current when ACC = VIL is 5.0uA 2. Maximum ICC specifications are tested with VCC = VCC max. 3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH . Typical specifications are for VCC= 3.0V. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested.
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SWITCHING TEST CIRCUITS TEST SPECIFICATIONS Test Condition Output Load Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 70 90 1 TTL gate 30 100 5 0.0-3.0 1.5 1.5 Unit pF ns V V V
DEVICE UNDER TEST
1.6K ohm +5V
CL
1.2K ohm
DIODES=IN3064 OR EQUIVALENT
KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State(High Z) OUTPUTS
SWITCHING TEST WAVEFORMS
3.0V
1.5V
Measurement Level
1.5V
0.0V INPUT
OUTPUT
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AC CHARACTERISTICS
SymbolDESCRIPTION tACC Address to output delay tCE tOE tDF tOH tRC tWC tCWC tAS tAH tDS tDH tVCS tCES tCEH tOES tOEH Chip enable to output delay Output enable to output delay OE# High to output float(Note1) Output hold time of from the rising edge of Address, CE#, or OE#, whichever happens first Read cycle time (Note 1) Write cycle time (Note 1)
(TA=-40 C to 85 C, VCC=2.7V~3.6V)
CONDITION CE#=VIL MAX OE#=VIL OE#=VIL MAX MAX MAX MIN MIN MIN MIN MIN MIN MIN MIN MIN 70 70 70 30 25 0 70 70 70 0 45 35 0 50 90 90 90 40 30 0 90 90 90 0 45 45 0 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Command write cycle time(Note 1) Address setup time Address hold time Data setup time Data hold time Vcc setup time(Note 1) Chip enable setup time Chip enable hold time Output enable setup time (Note 1) Output enable hold time (Note 1) Read Toggle & Data# Polling tWES WE# setup time tWEH WE# hold time tCEP CE# pulse width tCEPH CE# pulse width high tWP WE# pulse width tWPH WE# pulse width high tBAL Sector address hold time Note: 1.Not 100% Tested 2.tr = tf = 5ns
MIN MIN MIN MIN MIN MIN MIN MIN MIN MAX
0 0 10 0 0 35 30 30 30 50
0 0 10 0 0 45 30 45 30 50
ns ns ns ns ns ns ns ns ns us
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Figure 1. COMMAND WRITE OPERATION
VCC
3V
Addresses
VIH
ADD Valid
VIL tAS tAH
WE#
VIH VIL tOES tWPH tCWC
tWP
CE#
VIH VIL tCS tCH
OE#
VIH VIL VIH tDS tDH
Data
VIL
DIN
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READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS
tRC VIH
Addresses
VIL
ADD Valid
tCE VIH
CE#
VIL
VIH
WE#
VIL VIH VIL tOH tOEH tOE tDF
OE#
tACC
Outputs
VOH VOL
HIGH Z
DATA Valid
HIGH Z
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AC CHARACTERISTICS
Parameter tREADY1 tREADY2 tRP1 tRP2 tRH tRB1 tRB2 Description RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) RESET# Pulse Width (During Automatic Algorithms) RESET# High Time Before Read(See Note) RY/BY# Recovery Time(to CE#, OE# go low) RY/BY# Recovery Time(to WE# go low) MIN MIN MIN MIN 10 500 70 0 50 us ns ns ns ns RESET# Pulse Width (NOT During Automatic Algorithms) MIN MAX 500 ns Test Setup All Speed Options Unit MAX 20 us
Note:Not 100% tested
Figure 3. RESET# TIMING WAVEFORM
RY/BY#
CE#, OE#
tRH
RESET#
tRP2 tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY#
tRB1
CE#, OE#
WE#
tRB2
RESET#
tRP1
Reset Timing during Automatic Algorithms
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ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC tAS
Read Status Data
Address
XXXh
SA
XXXh for chip erase tAH
VA
VA
CE#
tCH tGHWL
OE#
tWP
tWHWH2
WE#
tCS tDS tDH
tWPH
55h Data
10h
In Progress Complete
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
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Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH
Write Data 55H
Write Data 80H
Write Data AAH
Write Data 55H
Write Data 10H
Data Poll from system YES
No
DATA = FFh ?
YES
Auto Erase Completed
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Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC tAS
Read Status Data
Address
2AAh
Sector Address 0
tAH
Sector Address 1
Sector Address n
VA
VA
CE#
tCH tGHWL
OE#
tBAL tWHWH2
tWP
WE#
tCS tDS tDH
tWPH
55h Data
30h
30h
30h
In Progress Complete
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
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Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH
Write Data 55H
Write Data 80H
Write Data AAH
Write Data 55H
Write Data 30H Sector Address
Last Sector to Erase ?
NO
YES Data Poll from System
NO Data=FFh? YES
Auto Sector Erase Completed
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Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
ERASE SUSPEND
Reading or Programming End YES Write Data 30H
NO
ERASE RESUME Continue Erase
Another Erase Suspend ? YES
NO
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Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
Program Command Sequence(last two cycle)
tWC tAS
Read Status Data (last two cycle)
Address
XXXh
PA
tAH
PA
PA
CE#
tCH tGHWL
OE#
tWP
tWHWH1
WE#
tCS tDS tDH
tWPH
A0h Data
PD
Status
DOUT
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
Figure 10. Accelerated Program Timing Diagram
(8.5V ~ 9.5V) VHH
ACC
VIL or VIH VIL or VIH
tVHH
tVHH
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Figure 11. CE# CONTROLLED PROGRAM TIMING WAVEFORM
XXX for program XXX for erase
PA for program SA for sector erase XXX for chip erase
Data# Polling Address
tWC tWH tAS tAH
PA
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tDS tDH
tCPH tBUSY
Q7 Data
tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
DOUT
RESET#
RY/BY#
NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence.
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH
Write Data 55H
Write Data A0H
Write Program Data/Address
Increment Address
Data Poll from system
No Verify Byte Ok ?
YES
No Last Address ?
YES
Auto Program Completed
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SECTOR GROUP PROTECT/CHIP UNPROTECTED Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECTED WAVEFORM (RESET# Control)
VID VIH
RESET#
SA, A6 A1, A0
Valid (note 2)
Valid (note 2)
Valid (note 2)
Sector Group Protect or Chip Unprotect Data
1us
Verify 40h Status
60h
60h
Sector Group Protect: 150us Chip Unprotect: Time out timing (note 1)
CE#
WE#
OE#
Note: 1. If TA range during 0 C to 70 C, the time out timing is 15ms. If TA range during -40 C to 85 C, the time out timing is 18ms. 2. For sector group protect A6=0, A1=1, A0=0 ; for chip unprotect A6=1, A1=1, A0=0
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Figure 14. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
12V 3V A9
tVLHT Verify
12V 3V OE#
tVLHT tWPP 1 tVLHT
WE#
tOESP
CE#
Data
tOE
01H
F0H
A21-A16
Sector Address
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Figure 15. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=VID, A9=VID, CE#=VIL A6=VIL
Activate WE Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL A9 should remain VID
.
No
Read from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed
Protect Another Sector?
Yes
Remove VID from A9 Write Reset Command
Sector Protection Complete
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Figure 16. CHIP UNPROTECTED TIMING WAVEFORM(A9, OE# Control)
A1
12V 3V A9
tVLHT
A6
Verify
12V 3V OE#
tVLHT tWPP 2 tVLHT
WE#
tOESP
CE#
Data
tOE
00H
F0H
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Figure 17. CHIP UNPROTECTED FLOWCHART(A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=VID CE#=VIL, A6=1
Activate WE# Pulse
Time Out Timing (note 1)
Increment PLSCNT
Set OE#=CE#=VIL A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device No
Increment Sector Addr
Data=00H?
No
PLSCNT=1000?
Yes No
Yes Device Failed
All sectors have been verified? Yes Remove VID from A9 Write Reset Command
Chip Unprotect Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
Note: 1. If TA range during 0 C to 70 C, the time out timing is 15ms. If TA range during -40 C to 85 C, the time out timing is 18ms.
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Figure 18. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECTED ALGORITHMS WITH RESET#=VID
START START PLSCNT=1 Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
PLSCNT=1
RESET#=VID
RESET#=VID
Wait 1us
Wait 1us
Temporary Sector Unprotect Mode
No
First Write Cycle=60h? Yes Set up sector address No Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0
First Write Cycle=60h? Yes
No
Temporary Sector Unprotect Mode
All sectors protected? Yes Set up first sector address
Wait 150us
Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Increment PLSCNT Read from sector address with A6=0, A1=1, A0=0 No
Reset PLSCNT=1
Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0
Time out timing (note 1)
Increment PLSCNT No PLSCNT=25? Data=01h?
Verify Sector Unprotect: Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0
Yes Device failed
Yes No Protect another sector? Yes No PLSCNT=1000?
Reset PLSCNT=1 Data=00h?
Sector Protect Algorithm
No Remove VID from RESET# Yes Device failed Write reset command Last sector verified? No Yes
Sector Protect complete
Sector Unprotect Algorithm
Yes Remove VID from RESET#
Write reset command
Sector Unprotect complete
Note: 1. If TA range during 0 C to 70 C, the time out timing is 15ms. If TA range during -40 C to 85 C, the time out timing is 18ms.
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Figure 19. TEMPORARY SECTOR GROUP UNPROTECTED WAVEFORMS
12V
RESET#
0 or 3V VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
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Figure 20. TEMPORARY SECTOR GROUP UNPROTECTED FLOWCHART
Start
RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again.
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Figure 21. SILICON ID READ TIMING WAVEFORM
VCC
5V VID VIH VIL
VIH VIL tACC tACC
ADD A9
ADD A0 A1
VIH VIL
VIH
ADD
VIL
CE#
VIH VIL
WE#
VIH VIL
tCE
OE#
VIH VIL
tOE tDF tOH tOH
VIH
DATA Q0-Q7
DATA OUT
VIL
DATA OUT A3H
C2H
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WRITE OPERATION STATUS Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
tACC tCE
VA
VA
CE#
tCH tOE
OE#
tOEH tDF
WE#
tOH
Q7 Q0-Q6
tOH
Status Data
Complement
True
Valid Data
High Z
Status Data
Status Data
True
Valid Data
High Z
RY/BY#
NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
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Figure 23. DATA# POLLING ALGORITHM
START
Read Q7~Q0 Add. = VA (1)
Q7 = Data ?
Yes
No
No
Q5 = 1 ?
Yes Read Q7~Q0 Add. = VA
Yes Q7 = Data ? (2) No
FAIL
PASS
Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
tACC tCE
VA
VA
VA
CE#
tCH tOE
OE#
tOEH tDF
WE#
tOH
Q6/Q2
tOH
Valid Status (first read)
Valid Status (second read)
Valid Data (stops toggling)
Valid Data
RY/BY#
NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
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Figure 25. TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
Toggle Bit Q6 =Toggle? YES
NO
NO Q5=1?
YES Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command
Program/Erase Operation Complete
Note: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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Figure 26. Q6 versus Q2
Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete
WE#
Q6
Q2
NOTES: The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
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ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 100,000 MIN. TYP.(2) 0.7 35 7 36 MAX. 15 50 210 108 UNITS sec sec us sec Cycles
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25 C,3.3V.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Set VIN=0 VOUT=0 VIN=0 TYP 6 8.5 7.5 MAX 7.5 12 9 UNIT pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25 C, f=1.0MHz
DATA RETENTION
Parameter Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV033A is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 5. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Select mode. The command is valid only when the device is in the CFI mode.
Table 5-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 Data (h) 51 52 59 02 00 40 00 00 00 00 00
Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none)
Table 5-2. CFI Mode: System Interface Data Values
Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N us) Typical timeout for maximum size buffer write (2N us) (not supported) Typical timeout for individual sector erase (2N ms) Typical timeout for full chip erase (2N ms) Maximum timeout for single word/byte write times (2N X Typ) Maximum timeout for maximum size buffer write times (2N X Typ) Maximum timeout for individual sector erase times (2N X Typ) Maximum timeout for full chip erase times (not supported) Address (h) (Byte Mode) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C Data (h) 27 36 00 00 04 00 0A 00 05 00 04 00
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Table 5-3. CFI Mode: Device Geometry Data Values
Description Device size (2N bytes) Flash device interface code (02=asynchronous x8/x16) Maximum number of bytes in multi-byte write (not supported) Number of erase sector regions Erase Sector Region 1 Information [2E,2D] = # of same-size sectors in region 1-1 [30, 2F] = sector size in multiples of 256-bytes Erase Sector Region 2 Information Address (h) (Byte Mode) 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Data (h) 16 00 00 00 00 01 3F 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
Erase Sector Region 3 Information
Erase Sector Region 4 Information
Table 5-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description Query-unique ASCII string "PRI" Address (h) (Byte Mode) 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 Data (h) 50 52 49 31 30 01 02 01 04 04 20 00 00
Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (0=not supported)
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ORDERING INFORMATION PLASTIC PACKAGE
PART NO. ACCESS TIME (ns) MX29LV033ATC-70 70 MX29LV033ATC-90 MX29LV033ATI-70 MX29LV033ATI-90 MX29LV033ATC-70G MX29LV033ATC-90G MX29LV033ATI-70G MX29LV033ATI-90G 90 70 90 70 90 70 90 OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX. (uA) 50 5 50 50 50 50 50 50 50 5 5 5 5 5 5 5 PACKAGE 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type) 40 Pin TSOP (Normal Type)
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PACKAGE INFORMATION
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Revision History
Rev. No. 1.0 Description 1. To added CFI related information 2. Removed "Unlock Bypass" information 3. Removed "Advanced Information" Page P1,12,51,52 All P1 Date SEP/20/2004
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